Fix page table compilation issues
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parent
8e160782ec
commit
8fc3dc237f
2 changed files with 10 additions and 17 deletions
18
src/main.zig
18
src/main.zig
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@ -5,20 +5,8 @@ const Console = @import("drivers/Console.zig");
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const debug = @import("debug.zig");
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const mem = @import("mem.zig");
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const UART_BASE: usize = 0x10000000;
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const MEMORY_START = @extern([*]u8, .{.name = "__memory_start"});
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fn uart_put(c: u8) void {
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const uart: *volatile u8 = @ptrFromInt(UART_BASE);
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uart.* = c;
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}
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fn print(s: []const u8) void {
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for (s) |c| {
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uart_put(c);
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}
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}
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pub const panic = debug.KernelPanic;
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export fn _start() linksection(".text.init") callconv(.naked) noreturn {
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@ -61,10 +49,8 @@ export fn kmain(hartid: u64, fdt_ptr: *const anyopaque) callconv(.c) noreturn {
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table.map(allocator, @intFromPtr(console.mmio), @intFromPtr(console.mmio), .{.read = 1, .write = 1, .execute = 1}, mmu_type) catch {
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};
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isa.write_satp(.{
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.ppn = @as(u44, @intCast(@intFromPtr(table) >> 12)),
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.mode = mmu_type,
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});
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table.load(mmu_type);
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debug.print("loaded kernel page table.\n", .{});
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while (true) {
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@ -50,6 +50,13 @@ pub fn identityMap(self: *PageTable, allocator: Allocator, memory_end: u64, mode
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}
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}
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pub fn load(self: *const PageTable, mmu_type: isa.Satp.Mode) void {
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isa.write_satp(.{
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.ppn = @as(u44, @intCast(@intFromPtr(self) >> 12)),
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.mode = mmu_type,
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});
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}
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pub fn map(self: *PageTable, allocator: Allocator, virtual: u64, physical: u64, flags: EntryFlags, mode: isa.Satp.Mode) !void {
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const PAGE_SIZE = 4096;
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@ -76,7 +83,7 @@ pub fn map(self: *PageTable, allocator: Allocator, virtual: u64, physical: u64,
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while (level > 0) : (level -= 1) {
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const index = vpn[level];
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var entry = ¤t_table.entries[index];
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const entry = ¤t_table.entries[index];
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if (entry.flags.valid == 0) {
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const new_table = try PageTable.init(allocator);
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