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No commits in common. "62fefbc836420992ca5f57185662bc39d539feff" and "8e160782ec5f35b9a9c5c31ef4f6b4e41ce97df7" have entirely different histories.
62fefbc836
...
8e160782ec
10 changed files with 166 additions and 481 deletions
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@ -12,15 +12,13 @@ pub fn build(b: *std.Build) void {
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const kernel = b.addExecutable(.{
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.name = "kernel",
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.root_module = b.createModule(.{
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.root_source_file = b.path("src/kernel.zig"),
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.root_source_file = b.path("src/main.zig"),
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.target = target,
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.optimize = optimize,
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.code_model = .medium,
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}),
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});
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kernel.root_module.addAssemblyFile(b.path("src/boot.S"));
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kernel.setLinkerScript(b.path("linker.ld"));
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b.installArtifact(kernel);
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93
linker.ld
93
linker.ld
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@ -1,86 +1,35 @@
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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KERNEL_PHYS_BASE = 0x80200000;
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KERNEL_VIRT_OFFSET = 0xffffffc000000000;
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BOOT_STACK_SIZE = 0x10000;
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KERNEL_STACK_SIZE = 0x10000;
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MEMORY
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{
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RAM (rwx) : ORIGIN = 0x80200000, LENGTH = 126M
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}
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SECTIONS
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{
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. = KERNEL_PHYS_BASE;
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.text : {
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*(.text.init)
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*(.text .text.*)
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} > RAM
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__boot_phys_start = .;
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.rodata : {
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*(.rodata .rodata.*)
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} > RAM
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.boot.text : ALIGN(0x1000) {
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*(.boot.text)
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*(.boot.text.*)
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}
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.data : {
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*(.data .data.*)
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} > RAM
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.boot.rodata : ALIGN(0x1000) {
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*(.boot.rodata)
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*(.boot.rodata.*)
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}
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.boot.data : ALIGN(0x1000) {
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*(.boot.data)
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*(.boot.data.*)
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}
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.boot.bss (NOLOAD) : ALIGN(0x1000) {
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*(.boot.bss)
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*(.boot.bss.*)
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}
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. = ALIGN(16);
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. += BOOT_STACK_SIZE;
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__boot_stack_top = .;
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. = ALIGN(0x1000);
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__boot_phys_end = .;
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__kernel_phys_start = .;
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. = KERNEL_VIRT_OFFSET + __kernel_phys_start;
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__kernel_start = .;
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__kernel_virt_start = .;
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.text : AT(ADDR(.text) - KERNEL_VIRT_OFFSET) ALIGN(0x1000) {
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*(.text)
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*(.text.*)
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}
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.rodata : AT(ADDR(.rodata) - KERNEL_VIRT_OFFSET) ALIGN(0x1000) {
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*(.rodata)
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*(.rodata.*)
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}
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.data : AT(ADDR(.data) - KERNEL_VIRT_OFFSET) ALIGN(0x1000) {
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PROVIDE(__global_pointer$ = . + 0x800);
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*(.data)
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*(.data.*)
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*(.sdata)
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*(.sdata.*)
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}
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.bss : AT(ADDR(.bss) - KERNEL_VIRT_OFFSET) ALIGN(0x1000) {
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.bss : {
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__bss_start = .;
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*(.bss)
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*(.bss.*)
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*(.sbss)
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*(.sbss.*)
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(16);
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. += KERNEL_STACK_SIZE;
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__stack_top = .;
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__bss_end = .;
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}
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} > RAM
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__kernel_end = ALIGN(., 0x1000);
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__kernel_virt_end = __kernel_end;
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__kernel_phys_end = __kernel_end - KERNEL_VIRT_OFFSET;
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__memory_start = __kernel_phys_end;
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/DISCARD/ : {
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*(.eh_frame)
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*(.eh_frame_hdr)
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}
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. = ALIGN(16);
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__stack_top = . + 0x10000;
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. = ALIGN(0x1000);
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PROVIDE(__memory_start = .);
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}
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83
src/Fdt.zig
83
src/Fdt.zig
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@ -468,19 +468,6 @@ pub fn parse(ptr: *const anyopaque) Error!Fdt {
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const size_dt_strings = std.mem.bigToNative(u32, header.size_dt_strings);
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const off_mem_rsvmap = std.mem.bigToNative(u32, header.off_mem_rsvmap);
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if (totalsize < @sizeOf(RawHeader)) {
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return Error.InvalidStructure;
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}
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if (!sliceWithinBounds(off_dt_struct, size_dt_struct, totalsize)) {
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return Error.InvalidStructure;
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}
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if (!sliceWithinBounds(off_dt_strings, size_dt_strings, totalsize)) {
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return Error.InvalidStructure;
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}
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if (off_mem_rsvmap > totalsize) {
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return Error.InvalidStructure;
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}
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return Fdt{
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.base = base,
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.totalsize = totalsize,
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@ -629,74 +616,11 @@ pub fn cpus(self: *const Fdt) ?Node {
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return self.findNode("/cpus");
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}
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pub fn parent(self: *const Fdt, target: Node) ?Node {
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var pos: usize = 0;
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var stack: [64]Node = undefined;
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var depth: usize = 0;
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while (pos < self.struct_block.len) {
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const token = self.readToken(pos) orelse return null;
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pos += 4;
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switch (token) {
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.begin_node => {
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const name_start = pos;
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while (pos < self.struct_block.len and self.struct_block[pos] != 0) {
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pos += 1;
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}
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if (pos >= self.struct_block.len) return null;
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const node = Node{
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.name = self.struct_block[name_start..pos],
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.fdt = self,
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.struct_offset = alignUp(pos + 1, 4),
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};
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pos = node.struct_offset;
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if (node.struct_offset == target.struct_offset and std.mem.eql(u8, node.name, target.name)) {
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if (depth == 0) return null;
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return stack[depth - 1];
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}
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if (depth >= stack.len) return null;
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stack[depth] = node;
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depth += 1;
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},
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.end_node => {
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if (depth == 0) return null;
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depth -= 1;
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},
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.prop => {
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const len = self.readU32(pos) orelse return null;
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pos += 8;
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pos += alignUp(len, 4);
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},
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.nop => {},
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.end => return null,
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}
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}
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return null;
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}
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pub fn regIterator(self: *const Fdt, node: Node) ?RegIterator {
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const reg = node.reg() orelse return null;
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const parent_node = self.parent(node) orelse self.root() orelse return null;
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return parseReg(reg, parent_node.addressCells(), parent_node.sizeCells());
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}
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// Internal helpers
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fn readToken(self: *const Fdt, offset: usize) ?Token {
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if (offset + 4 > self.struct_block.len) return null;
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const val = std.mem.bigToNative(u32, @as(*const u32, @alignCast(@ptrCast(self.struct_block.ptr + offset))).*);
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return switch (val) {
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@intFromEnum(Token.begin_node) => .begin_node,
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@intFromEnum(Token.end_node) => .end_node,
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@intFromEnum(Token.prop) => .prop,
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@intFromEnum(Token.nop) => .nop,
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@intFromEnum(Token.end) => .end,
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else => null,
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};
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return @as(Token, @enumFromInt(val));
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}
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fn readU32(self: *const Fdt, offset: usize) ?u32 {
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@ -749,11 +673,6 @@ fn alignUp(value: anytype, alignment: @TypeOf(value)) @TypeOf(value) {
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return (value + alignment - 1) & ~(alignment - 1);
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}
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fn sliceWithinBounds(offset: u32, size: u32, total: u32) bool {
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const end = @as(u64, offset) + @as(u64, size);
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return end <= total;
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}
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pub fn parseReg(data: []const u8, address_cells: u32, size_cells: u32) RegIterator {
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return .{
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.data = data,
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90
src/boot.S
90
src/boot.S
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@ -1,90 +0,0 @@
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.section .boot.text, "ax", @progbits
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.globl _start
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.equ PTE_VALID, 0x001
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.equ PTE_READ, 0x002
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.equ PTE_WRITE, 0x004
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.equ PTE_EXECUTE, 0x008
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.equ PTE_FLAGS, PTE_VALID | PTE_READ | PTE_WRITE | PTE_EXECUTE
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.equ SATP_MODE_SV39, (8 << 60)
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.equ LOW_RAM_ROOT_INDEX, (2 * 8)
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.equ KERNEL_ROOT_INDEX, (0x102 * 8)
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.equ PHYSMAP_ROOT_INDEX, (0x142 * 8)
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.equ MMIO_ROOT_INDEX, (0x180 * 8)
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.equ LOW_RAM_GIGAPAGE_PTE, 0x2000000f
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.equ ZERO_GIGAPAGE_PTE, 0x0000000f
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.equ UART_PHYS, 0x10000000
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_start:
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li fp, 0
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li ra, 0
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la sp, __boot_stack_top
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la t0, boot_root_page
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li t1, LOW_RAM_GIGAPAGE_PTE
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sd t1, LOW_RAM_ROOT_INDEX(t0)
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li t2, PHYSMAP_ROOT_INDEX
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add t2, t2, t0
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sd t1, 0(t2)
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li t1, LOW_RAM_GIGAPAGE_PTE
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li t2, KERNEL_ROOT_INDEX
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add t2, t2, t0
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sd t1, 0(t2)
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li t1, ZERO_GIGAPAGE_PTE
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li t2, MMIO_ROOT_INDEX
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add t2, t2, t0
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sd t1, 0(t2)
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srli t1, t0, 12
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li t2, SATP_MODE_SV39
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or t1, t1, t2
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csrw satp, t1
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sfence.vma
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li a2, UART_PHYS
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la t3, memory_start_ptr
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ld a3, 0(t3)
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li a4, 0
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la t3, bss_start_ptr
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ld t0, 0(t3)
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la t3, bss_end_ptr
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ld t1, 0(t3)
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bgeu t0, t1, 2f
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1:
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sd zero, 0(t0)
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addi t0, t0, 8
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bltu t0, t1, 1b
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2:
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la t3, stack_top_ptr
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ld sp, 0(t3)
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la t3, global_pointer_ptr
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ld gp, 0(t3)
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li fp, 0
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la t3, kmain_ptr
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ld t0, 0(t3)
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jr t0
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.section .boot.rodata, "a", @progbits
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.balign 8
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memory_start_ptr:
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.dword __memory_start
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bss_start_ptr:
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.dword __bss_start
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bss_end_ptr:
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.dword __bss_end
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stack_top_ptr:
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.dword __stack_top
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global_pointer_ptr:
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.dword __global_pointer$
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kmain_ptr:
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.dword kmain
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.section .boot.bss, "aw", @nobits
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.balign 4096
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boot_root_page:
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.skip 4096
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@ -2,35 +2,47 @@ const std = @import("std");
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const Fdt = @import("../Fdt.zig");
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const Console = @This();
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mmio: *volatile u8,
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pub const Writer = struct {
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base: *volatile u8,
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interface: std.Io.Writer,
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pub fn initAt(address: usize) Console {
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return .{
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.mmio = @ptrFromInt(address),
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};
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pub fn drain(io_w: *std.Io.Writer, data: []const []const u8, splat: usize) !usize {
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_ = splat;
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const self: *Writer = @fieldParentPtr("interface", io_w);
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self.base.* = data[0][0];
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return data.len;
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}
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};
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mmio: *volatile u8,
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pub fn init(fdt: Fdt) ?Console {
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if (fdt.findFirstCompatible("ns16550a")) |console| {
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var iter = fdt.regIterator(console) orelse return null;
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const start = iter.next().?.address;
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return initAt(@as(usize, @intCast(start)));
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var iter = console.getProperty("reg").?.asU32Array();
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_ = iter.next();
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const start = iter.next().?;
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return .{
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.mmio = @ptrFromInt(@as(usize, @intCast(start))),
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};
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}
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return null;
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}
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pub fn write(self: *const Console, bytes: []const u8) void {
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for (bytes) |byte| {
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self.mmio.* = byte;
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}
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pub fn writer(self: *const Console) Writer {
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return .{
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.base = self.mmio,
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.interface = std.Io.Writer {
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.buffer = &[_]u8{},
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.vtable = &.{.drain = Writer.drain},
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},
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};
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}
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pub fn print(self: *const Console, comptime s: []const u8, args: anytype) void {
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var buffer: [512]u8 = undefined;
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const formatted = std.fmt.bufPrint(&buffer, s, args) catch {
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self.write("debug print overflow\n");
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return;
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var w = self.writer();
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w.interface.print(s, args) catch {
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@panic("Failed to print debug message.\n");
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};
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self.write(formatted);
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}
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|
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@ -1,96 +0,0 @@
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const std = @import("std");
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const Fdt = @import("Fdt.zig");
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const Console = @import("drivers/Console.zig");
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const debug = @import("debug.zig");
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const mem = @import("mem.zig");
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const isa = @import("riscv/isa.zig");
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const KERNEL_PHYS_BASE: u64 = 0x80200000;
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pub const panic = debug.KernelPanic;
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pub export fn kmain(hartid: u64, fdt_phys: usize, console_phys: usize, alloc_start_phys: usize, memory_end_hint: usize) callconv(.c) noreturn {
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_ = hartid;
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const console = Console.initAt(@intCast(mem.physToMmioVirt(console_phys)));
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debug.init(console);
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debug.print("entered higher-half kernel.\n", .{});
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const fdt = Fdt.parse(@ptrFromInt(mem.physToDirectMap(fdt_phys))) catch {
|
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@panic("Unable to parse higher-half FDT.\n");
|
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};
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debug.print("fdt remapped at 0x{x}.\n", .{mem.physToDirectMap(fdt_phys)});
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|
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const root = fdt.root().?;
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const memory = fdt.memory().?;
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var reg_iter = Fdt.parseReg(memory.getProperty("reg").?.data, root.addressCells(), root.sizeCells());
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const reg = reg_iter.next().?;
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const detected_memory_end = reg.address + reg.size;
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const memory_end = if (memory_end_hint != 0) @min(detected_memory_end, memory_end_hint) else detected_memory_end;
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debug.print("detected RAM end at 0x{x}.\n", .{memory_end});
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var buddy: mem.BuddyAllocator = .{};
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const alloc_start = mem.physToDirectMap(alloc_start_phys);
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buddy.init(@as([*]u8, @ptrFromInt(alloc_start))[0..memory_end - alloc_start_phys]);
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debug.print("direct map allocator initialized.\n", .{});
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const allocator = buddy.allocator();
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const mmu_type = fdt.mmuType();
|
||||
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if (mmu_type != .bare) {
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var table = isa.PageTable.init(allocator) catch {
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@panic("Unable to allocate higher-half page table.\n");
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||||
};
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||||
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const kernel_flags: isa.PageTable.EntryFlags = .{
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.valid = 1,
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.read = 1,
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.write = 1,
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.execute = 1,
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.user = 0,
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};
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table.mapRange(
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allocator,
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||||
mem.physToKernelVirt(KERNEL_PHYS_BASE),
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KERNEL_PHYS_BASE,
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alloc_start_phys - KERNEL_PHYS_BASE,
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kernel_flags,
|
||||
mmu_type,
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||||
mem.PHYS_MAP_BASE,
|
||||
) catch {
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||||
@panic("Unable to map higher-half kernel image.\n");
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||||
};
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||||
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||||
table.mapRange(
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allocator,
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||||
mem.physToDirectMap(reg.address),
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||||
reg.address,
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||||
memory_end - reg.address,
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||||
.{ .read = 1, .write = 1, .execute = 1 },
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mmu_type,
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mem.PHYS_MAP_BASE,
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||||
) catch {
|
||||
@panic("Unable to map direct map window.\n");
|
||||
};
|
||||
|
||||
const console_page = std.mem.alignBackward(u64, @intCast(console_phys), mem.PAGE_SIZE);
|
||||
table.map(
|
||||
allocator,
|
||||
mem.physToMmioVirt(console_page),
|
||||
console_page,
|
||||
.{ .read = 1, .write = 1, .execute = 1 },
|
||||
mmu_type,
|
||||
mem.PHYS_MAP_BASE,
|
||||
) catch {
|
||||
@panic("Unable to map console MMIO.\n");
|
||||
};
|
||||
|
||||
table.load(mmu_type, mem.PHYS_MAP_BASE);
|
||||
debug.print("reloaded higher-half kernel page table.\n", .{});
|
||||
}
|
||||
|
||||
while (true) {
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
}
|
||||
73
src/main.zig
Normal file
73
src/main.zig
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
const std = @import("std");
|
||||
const isa = @import("riscv/isa.zig");
|
||||
const Fdt = @import("Fdt.zig");
|
||||
const Console = @import("drivers/Console.zig");
|
||||
const debug = @import("debug.zig");
|
||||
const mem = @import("mem.zig");
|
||||
|
||||
const UART_BASE: usize = 0x10000000;
|
||||
const MEMORY_START = @extern([*]u8, .{.name = "__memory_start"});
|
||||
|
||||
fn uart_put(c: u8) void {
|
||||
const uart: *volatile u8 = @ptrFromInt(UART_BASE);
|
||||
uart.* = c;
|
||||
}
|
||||
|
||||
fn print(s: []const u8) void {
|
||||
for (s) |c| {
|
||||
uart_put(c);
|
||||
}
|
||||
}
|
||||
|
||||
pub const panic = debug.KernelPanic;
|
||||
|
||||
export fn _start() linksection(".text.init") callconv(.naked) noreturn {
|
||||
asm volatile (
|
||||
\\li fp, 0
|
||||
\\li ra, 0
|
||||
\\li sp, 0x88000000
|
||||
\\tail kmain
|
||||
);
|
||||
}
|
||||
|
||||
export fn kmain(hartid: u64, fdt_ptr: *const anyopaque) callconv(.c) noreturn {
|
||||
_ = hartid;
|
||||
|
||||
const fdt = Fdt.parse(fdt_ptr) catch {
|
||||
while (true) asm volatile ("wfi");
|
||||
};
|
||||
|
||||
const root = fdt.root().?;
|
||||
|
||||
const console = Console.init(fdt).?;
|
||||
debug.init(console);
|
||||
|
||||
debug.print("booting hydra...\n", .{});
|
||||
|
||||
const memory = fdt.memory().?;
|
||||
var reg_iter = Fdt.parseReg(memory.getProperty("reg").?.data, root.addressCells(), root.sizeCells());
|
||||
const reg = reg_iter.next().?;
|
||||
const memory_end = reg.address + reg.size;
|
||||
|
||||
var buddy: mem.BuddyAllocator = .{};
|
||||
buddy.init(MEMORY_START[0..memory_end - @intFromPtr(MEMORY_START)]);
|
||||
debug.print("memory allocator initialized.\n", .{});
|
||||
|
||||
const allocator = buddy.allocator();
|
||||
const mmu_type = fdt.mmuType();
|
||||
|
||||
var table = isa.PageTable.init(allocator) catch { @panic("Unable to create page table.\n"); };
|
||||
table.identityMap(allocator, memory_end, mmu_type) catch {};
|
||||
table.map(allocator, @intFromPtr(console.mmio), @intFromPtr(console.mmio), .{.read = 1, .write = 1, .execute = 1}, mmu_type) catch {
|
||||
|
||||
};
|
||||
isa.write_satp(.{
|
||||
.ppn = @as(u44, @intCast(@intFromPtr(table) >> 12)),
|
||||
.mode = mmu_type,
|
||||
});
|
||||
debug.print("loaded kernel page table.\n", .{});
|
||||
|
||||
while (true) {
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
}
|
||||
19
src/mem.zig
19
src/mem.zig
|
|
@ -1,22 +1,3 @@
|
|||
pub const BuddyAllocator = @import("mem/BuddyAllocator.zig");
|
||||
|
||||
pub const PAGE_SIZE = 0x1000;
|
||||
pub const KERNEL_VIRT_OFFSET: u64 = 0xffffffc000000000;
|
||||
pub const PHYS_MAP_BASE: u64 = 0xffffffd000000000;
|
||||
pub const MMIO_VIRT_OFFSET: u64 = 0xffffffe000000000;
|
||||
|
||||
pub fn physToKernelVirt(physical: u64) u64 {
|
||||
return KERNEL_VIRT_OFFSET + physical;
|
||||
}
|
||||
|
||||
pub fn physToDirectMap(physical: u64) u64 {
|
||||
return PHYS_MAP_BASE + physical;
|
||||
}
|
||||
|
||||
pub fn directMapToPhys(virtual: u64) u64 {
|
||||
return virtual - PHYS_MAP_BASE;
|
||||
}
|
||||
|
||||
pub fn physToMmioVirt(physical: u64) u64 {
|
||||
return MMIO_VIRT_OFFSET + physical;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,11 +22,6 @@ fn getLevelSize(level: u8) usize {
|
|||
return @as(usize, MIN_BLOCK_SIZE) << @intCast(level);
|
||||
}
|
||||
|
||||
fn levelForRequest(len: usize, alignment: std.mem.Alignment) usize {
|
||||
const required_size = @max(@max(len, MIN_BLOCK_SIZE), alignment.toByteUnits());
|
||||
return math.log2_int_ceil(usize, (required_size + MIN_BLOCK_SIZE - 1) / MIN_BLOCK_SIZE);
|
||||
}
|
||||
|
||||
pub fn freeRange(self: *BuddyAllocator, start: [*]u8, size: usize) void {
|
||||
var current_addr = @intFromPtr(start);
|
||||
const end_addr = current_addr + size;
|
||||
|
|
@ -124,15 +119,23 @@ pub fn allocator(self: *BuddyAllocator) Allocator {
|
|||
}
|
||||
|
||||
fn alloc(ctx: *anyopaque, len: usize, ptr_align: std.mem.Alignment, ret_addr: usize) ?[*]u8 {
|
||||
_ = ptr_align;
|
||||
_ = ret_addr;
|
||||
const self: *BuddyAllocator = @ptrCast(@alignCast(ctx));
|
||||
|
||||
return self.allocBlock(@intCast(levelForRequest(len, ptr_align)));
|
||||
const actual_size = @max(len, MIN_BLOCK_SIZE);
|
||||
const level = math.log2_int_ceil(usize, (actual_size + MIN_BLOCK_SIZE - 1) / MIN_BLOCK_SIZE);
|
||||
|
||||
return self.allocBlock(@intCast(level));
|
||||
}
|
||||
|
||||
fn free(ctx: *anyopaque, buf: []u8, buf_align: std.mem.Alignment, ret_addr: usize) void {
|
||||
_ = buf_align;
|
||||
_ = ret_addr;
|
||||
const self: *BuddyAllocator = @ptrCast(@alignCast(ctx));
|
||||
|
||||
self.freeBlock(buf.ptr, @intCast(levelForRequest(buf.len, buf_align)));
|
||||
const actual_size = @max(buf.len, MIN_BLOCK_SIZE);
|
||||
const level = math.log2_int_ceil(usize, (actual_size + MIN_BLOCK_SIZE - 1) / MIN_BLOCK_SIZE);
|
||||
|
||||
self.freeBlock(buf.ptr, @intCast(level));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,11 @@
|
|||
const std = @import("std");
|
||||
const Allocator = std.mem.Allocator;
|
||||
const PageTable = @This();
|
||||
const debug = @import("../debug.zig");
|
||||
const isa = @import("isa.zig");
|
||||
|
||||
const MEMORY_START = @extern([*]u8, .{.name = "__memory_start"});
|
||||
|
||||
pub const EntryFlags = packed struct {
|
||||
valid: u1 = 1,
|
||||
read: u1,
|
||||
|
|
@ -22,21 +25,17 @@ pub const Entry = packed struct {
|
|||
n: u1 = 0,
|
||||
};
|
||||
|
||||
const PTE_VALID = @as(u64, 1) << 0;
|
||||
const PTE_READ = @as(u64, 1) << 1;
|
||||
const PTE_WRITE = @as(u64, 1) << 2;
|
||||
const PTE_EXECUTE = @as(u64, 1) << 3;
|
||||
const PTE_USER = @as(u64, 1) << 4;
|
||||
|
||||
entries: [512]u64,
|
||||
entries: [512]Entry,
|
||||
|
||||
pub fn init(allocator: Allocator) !*PageTable {
|
||||
const table = try allocator.create(PageTable);
|
||||
@memset(&table.entries, 0);
|
||||
for (&table.entries) |*entry| {
|
||||
entry.* = @bitCast(@as(u64, 0x0));
|
||||
}
|
||||
return table;
|
||||
}
|
||||
|
||||
pub fn identityMap(self: *PageTable, allocator: Allocator, start: u64, end: u64, mode: isa.Satp.Mode, direct_map_base: u64) !void {
|
||||
pub fn identityMap(self: *PageTable, allocator: Allocator, memory_end: u64, mode: isa.Satp.Mode) !void {
|
||||
const flags = EntryFlags{
|
||||
.valid = 1,
|
||||
.read = 1,
|
||||
|
|
@ -45,53 +44,16 @@ pub fn identityMap(self: *PageTable, allocator: Allocator, start: u64, end: u64,
|
|||
.user = 0,
|
||||
};
|
||||
|
||||
return self.mapRange(allocator, start, start, end - start, flags, mode, direct_map_base);
|
||||
}
|
||||
|
||||
pub fn mapRange(self: *PageTable, allocator: Allocator, virtual_start: u64, physical_start: u64, length: u64, flags: EntryFlags, mode: isa.Satp.Mode, direct_map_base: u64) !void {
|
||||
if (length == 0) return;
|
||||
|
||||
var virtual = virtual_start;
|
||||
var physical = physical_start;
|
||||
const virtual_end = virtual_start + length;
|
||||
|
||||
while (virtual < virtual_end) {
|
||||
const remaining = virtual_end - virtual;
|
||||
if (virtual % (2 * 1024 * 1024) == 0 and physical % (2 * 1024 * 1024) == 0 and remaining >= 2 * 1024 * 1024) {
|
||||
try self.mapLarge2MiB(allocator, virtual, physical, flags, mode, direct_map_base);
|
||||
virtual += 2 * 1024 * 1024;
|
||||
physical += 2 * 1024 * 1024;
|
||||
} else {
|
||||
try self.map(allocator, virtual, physical, flags, mode, direct_map_base);
|
||||
virtual += 0x1000;
|
||||
physical += 0x1000;
|
||||
}
|
||||
var addr: u64 = 0x0;
|
||||
while (addr < memory_end) : (addr += 0x1000) {
|
||||
try self.map(allocator, addr, addr, flags, mode);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn load(self: *const PageTable, mmu_type: isa.Satp.Mode, direct_map_base: u64) void {
|
||||
isa.write_satp(.{
|
||||
.ppn = @as(u44, @intCast(pointerToPhysical(@intFromPtr(self), direct_map_base) >> 12)),
|
||||
.mode = mmu_type,
|
||||
});
|
||||
}
|
||||
pub fn map(self: *PageTable, allocator: Allocator, virtual: u64, physical: u64, flags: EntryFlags, mode: isa.Satp.Mode) !void {
|
||||
const PAGE_SIZE = 4096;
|
||||
|
||||
pub fn map(self: *PageTable, allocator: Allocator, virtual: u64, physical: u64, flags: EntryFlags, mode: isa.Satp.Mode, direct_map_base: u64) !void {
|
||||
return self.mapAtLevel(allocator, virtual, physical, flags, mode, 0, direct_map_base);
|
||||
}
|
||||
|
||||
pub fn mapLarge2MiB(self: *PageTable, allocator: Allocator, virtual: u64, physical: u64, flags: EntryFlags, mode: isa.Satp.Mode, direct_map_base: u64) !void {
|
||||
return self.mapAtLevel(allocator, virtual, physical, flags, mode, 1, direct_map_base);
|
||||
}
|
||||
|
||||
fn mapAtLevel(self: *PageTable, allocator: Allocator, virtual: u64, physical: u64, flags: EntryFlags, mode: isa.Satp.Mode, leaf_level: usize, direct_map_base: u64) !void {
|
||||
const page_size: u64 = switch (leaf_level) {
|
||||
0 => 4096,
|
||||
1 => 2 * 1024 * 1024,
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
if (virtual % page_size != 0 or physical % page_size != 0) {
|
||||
if (virtual % PAGE_SIZE != 0 or physical % PAGE_SIZE != 0) {
|
||||
return error.AddressNotAligned;
|
||||
}
|
||||
|
||||
|
|
@ -112,52 +74,26 @@ fn mapAtLevel(self: *PageTable, allocator: Allocator, virtual: u64, physical: u6
|
|||
|
||||
var current_table = self;
|
||||
|
||||
while (level > leaf_level) : (level -= 1) {
|
||||
while (level > 0) : (level -= 1) {
|
||||
const index = vpn[level];
|
||||
const entry = ¤t_table.entries[index];
|
||||
var entry = ¤t_table.entries[index];
|
||||
|
||||
if (!isValid(entry.*)) {
|
||||
if (entry.flags.valid == 0) {
|
||||
const new_table = try PageTable.init(allocator);
|
||||
|
||||
const table_phys = pointerToPhysical(@intFromPtr(new_table), direct_map_base);
|
||||
entry.* = encodeBranchEntry(table_phys);
|
||||
const table_phys = @intFromPtr(new_table);
|
||||
entry.* = .{
|
||||
.flags = .{ .valid = 1, .read = 0, .write = 0, .execute = 0, .user = 0 },
|
||||
.ppn = @truncate(table_phys >> 12),
|
||||
};
|
||||
}
|
||||
|
||||
const next_table_phys = decodePhysical(entry.*);
|
||||
current_table = @ptrFromInt(physicalToPointer(next_table_phys, direct_map_base));
|
||||
const next_table_phys = @as(u64, entry.ppn) << 12;
|
||||
current_table = @ptrFromInt(next_table_phys);
|
||||
}
|
||||
|
||||
current_table.entries[vpn[leaf_level]] = encodeLeafEntry(physical, flags);
|
||||
}
|
||||
|
||||
fn pointerToPhysical(pointer: u64, direct_map_base: u64) u64 {
|
||||
if (direct_map_base == 0) return pointer;
|
||||
return pointer - direct_map_base;
|
||||
}
|
||||
|
||||
fn physicalToPointer(physical: u64, direct_map_base: u64) u64 {
|
||||
if (direct_map_base == 0) return physical;
|
||||
return physical + direct_map_base;
|
||||
}
|
||||
|
||||
fn isValid(entry: u64) bool {
|
||||
return (entry & PTE_VALID) != 0;
|
||||
}
|
||||
|
||||
fn decodePhysical(entry: u64) u64 {
|
||||
return ((entry >> 10) & ((@as(u64, 1) << 44) - 1)) << 12;
|
||||
}
|
||||
|
||||
fn encodeBranchEntry(physical: u64) u64 {
|
||||
return PTE_VALID | ((physical >> 12) << 10);
|
||||
}
|
||||
|
||||
fn encodeLeafEntry(physical: u64, flags: EntryFlags) u64 {
|
||||
var entry = (physical >> 12) << 10;
|
||||
entry |= PTE_VALID;
|
||||
if (flags.read != 0) entry |= PTE_READ;
|
||||
if (flags.write != 0) entry |= PTE_WRITE;
|
||||
if (flags.execute != 0) entry |= PTE_EXECUTE;
|
||||
if (flags.user != 0) entry |= PTE_USER;
|
||||
return entry;
|
||||
current_table.entries[vpn[0]] = .{
|
||||
.flags = flags,
|
||||
.ppn = @truncate(physical >> 12),
|
||||
};
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue