66 lines
1.9 KiB
Zig
66 lines
1.9 KiB
Zig
const std = @import("std");
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const isa = @import("riscv/isa.zig");
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const Fdt = @import("Fdt.zig");
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const Console = @import("drivers/Console.zig");
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const debug = @import("debug.zig");
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const mem = @import("mem.zig");
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const UART_BASE: usize = 0x10000000;
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const MEMORY_START = @extern([*]u8, .{.name = "__memory_start"});
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fn uart_put(c: u8) void {
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const uart: *volatile u8 = @ptrFromInt(UART_BASE);
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uart.* = c;
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}
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fn print(s: []const u8) void {
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for (s) |c| {
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uart_put(c);
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}
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}
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export fn _start() linksection(".text.init") callconv(.naked) noreturn {
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asm volatile (
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\\li sp, 0x88000000
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\\tail kmain
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);
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}
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export fn kmain(hartid: u64, fdt_ptr: *const anyopaque) callconv(.c) noreturn {
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_ = hartid;
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const fdt = Fdt.parse(fdt_ptr) catch {
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while (true) asm volatile ("wfi");
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};
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const root = fdt.root().?;
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const console = Console.init(fdt).?;
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debug.init(console);
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debug.print("booting hydra...\n", .{});
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const memory = fdt.memory().?;
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var reg_iter = Fdt.parseReg(memory.getProperty("reg").?.data, root.addressCells(), root.sizeCells());
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const reg = reg_iter.next().?;
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const memory_end = reg.address + reg.size;
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var buddy: mem.BuddyAllocator = .{};
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buddy.init(MEMORY_START[0..memory_end - @intFromPtr(MEMORY_START)]);
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debug.print("memory allocator initialized.\n", .{});
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const allocator = buddy.allocator();
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var table = isa.PageTable.init(allocator) catch { @panic("Unable to create page table.\n"); };
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table.identityMap(allocator, memory_end) catch {};
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table.map(allocator, @intFromPtr(console.mmio), @intFromPtr(console.mmio), .{.read = 1, .write = 1, .execute = 1}) catch {};
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isa.write_satp(.{
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.ppn = @as(u44, @intCast(@intFromPtr(table) >> 12)),
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.mode = .sv57,
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});
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debug.print("loaded kernel page table.\n", .{});
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while (true) {
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asm volatile ("wfi");
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}
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}
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